In a recent semiconductor circuit, through refining techniques of a transistor having a MOS (Metal Oxide Semiconductor) structure, it has become possible to integrate more than one million transistors on a single chip. Further, a Bi-CMOS device having bipolar and CMOS (Complementary MOS) elements lying mixed on a single chip has frequently been used to display their features respectively.
In the Bi-CMOS circuit, a high-speed operable ECL (Emitter Coupled Logic) circuit and a CMOS circuit of low power consumption is combined so that a high speed logic circuit of low power consumption can be realized. As an application of such a Bi-CMOS circuit, a high speed SRAM (Static Random Access Memory) of low power consumption has been proposed by Takada et al (see "A 5 ns 1 Mb BiCMOS SRAM" ISSCC DIGEST of TECHNICAL PAPERS, pp 138-139, 1990).
FIG. 1 illustrates a general peripheral and read circuits of the SRAM. The read-out operation from a memory cell MC is made such that the bit lines B and B are first clamped to approximately the power voltage level Vcc (common signal level), and then the data signal is read out from the memory cell MC to the bit lines B and B as a small voltage difference from the common signal level, the voltage difference being about several tens of millivolts (mV). The signal which is expressed as the small voltage difference is entered to a sense circuit through gates MP3 and MP4. That sense circuit comprises a two-stage wired-OR logic circuit and a cascode sense amplifier. Each wired-OR circuit comprises an emitter follower circuit of the bipolar transistor, providing the voltage shift equal to the base-to-emitter voltage Vf of the transistor when turned ON. The emitter follower circuits are provided in two stages for the purpose of shifting the voltage level of 2 Vf to stably operate the cascode type sense amplifier. The cascode type amplifier is comprised of a differential sense circuit (or a voltage-to-current converting sense circuit), a signal transmission bus line RB, and a current-to-voltage converting sense circuit. A high speed sensing can be achieved by driving the long bus line RB in the current mode.
The signal read out from the memory cell MC is shifted in voltage level by the two-stage wire-OR circuit to be input to each base of the transistors Q5 and Q6 of the differential sense circuit. Therefore, the potential Va of the common emitter terminal VA of the transistors Q5 and Q6 becomes approximately the voltage of (Vcc-3 Vf), where Vcc denotes the power supply voltage and Vf the base-to-emitter voltage of one of the bipolar transistors Q1 through Q6 when turned ON. Since this base-to-emitter voltage Vf is about 0.8 to 0.9 (V) , the potential Va of the common emitter terminal VA becomes about the voltage of (Vcc-2.7). Hence, if the source-to-drain voltage of the field effect transistor MN4 working as a constant current source is taken into account, it can be seen that, if the power supply voltage Vcc is set to a low voltage of 3.0 V, the cascode type sense amplifier ends up in an approximately inoperable state.